About me
I am an MSc graduate in Biomedical Engineering from ETH Zürich, specializing in mixed-signal integrated circuit design, neural interfaces, and FPGA-based data acquisition systems. My work spans analog front-end design in advanced CMOS nodes, embedded and firmware-level reliability, and high-throughput digital signal streaming.
Through research and teaching roles at ETH Zürich, I have contributed to the design of a 22 nm neural recording front-end with 256 channels, leading to an ISSCC submission, and have supported graduate-level courses in neuromorphic engineering and energy-efficient analog circuits. I am particularly interested in bridging electronics and neuroscience through robust, low-power hardware systems.
Resume
Education
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ETH Zürich - MSc Biomedical Engineering
2022 — 2025During my master’s studies, I specialized in mixed-signal integrated circuit design, neuromorphic engineering, and FPGA-based data acquisition systems, with a strong focus on low-power and high-performance hardware for biomedical applications. My coursework covered advanced analog and digital IC design, VLSI systems, machine learning fundamentals, and bioelectronics, complemented by extensive hands-on project and laboratory work.
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Politecnico di Milano - BSc Biomedical Engineering
2019 — 2022During my bachelor’s studies, I built a solid foundation in biomedical engineering, electronics, signal processing, and physiology, with a particular emphasis on the development of medical and biomedical devices. I gained early exposure to designing systems under regulatory and safety constraints, learning how biomedical applications must comply with standards, validation procedures, and reliability requirements.
In parallel, I was actively engaged in student associations focused on open-source software and Linux-based systems. Through this involvement, I developed practical skills in collaborative software development, open-source tools, and low-level system environments, which strengthened my interest in engineering solutions that are transparent, reproducible, and robust. This experience played a key role in shaping my later focus on hardware–software co-design and research-oriented engineering.
Experience
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Project Manager and IT Support - World Economic Forum
January 2026On behalf of the company Richnerstutz, I was responsible for the installation and deployment of IT infrastructure for clients, including network connectivity, printers, and end-user devices, ensuring full operational readiness ahead of the forum. During the event, I remained continuously on call to troubleshoot hardware, network, and device-related issues under time-critical conditions.
In addition to reactive support, I proactively engaged with clients, unprompted, to verify system functionality and address potential issues before they escalated. After the forum, I contributed to the systematic teardown and decommissioning of the installed infrastructure. This role required reliability, adaptability, and confident direct interaction with high-profile international stakeholders.
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Research Assistant - ETH Zürich
July 2025 — November 2025As a research assistant, I contributed to the design and characterization of a novel analog front-end for neural recording in a 22 nm CMOS technology. My work focused on capacitively coupled microelectrode arrays, enabling simultaneous acquisition from 256 channels at 10 µm pitch. I was involved in circuit-level design, system characterization, and experimental validation, contributing to results submitted to ISSCC 2026.
This role required close collaboration with researchers across analog design, bioelectronics, and experimental neuroscience, strengthening my ability to work effectively in interdisciplinary R&D environments.
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Teaching Assistant - ETH Zürich
2023 — 2025I supported multiple graduate-level courses, including Neuromorphic Engineering and Energy-Efficient Analog Integrated Circuits for IoT Systems. My responsibilities included assisting during lectures, interacting directly with students to clarify complex theoretical and practical concepts, and supporting their understanding of advanced analog and mixed-signal design techniques. This experience strengthened my technical communication skills and my ability to explain complex engineering topics clearly and effectively.
Projects
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Master's Thesis: High-Speed Neural Data Streaming Platform
I designed and implemented a complete digital acquisition and streaming platform to interface with a capacitive neural recording system. The work focused on reliably capturing 16-bit data from 16 parallel channels sampled at 20 kHz and streaming the resulting ≈6.4 Mbit/s data rate in real time.
The system was implemented on an AMD-Xilinx Kintex-7 FPGA using SystemVerilog, including clocking, synchronization, and high-speed serial data handling. On the host side, I developed a Python-based software interface to receive the data stream and efficiently write raw samples to memory for further processing.
This project required careful hardware–software co-design, attention to timing constraints, and robustness in continuous long-duration acquisition scenarios typical of neural recording experiments.
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Semester's Thesis: Redundant sensor driver reluing solely on Firmware
In this project, I implemented a firmware-based redundancy strategy to improve system robustness against transient faults and radiation-induced errors, targeting aerospace-oriented embedded applications. The solution relied exclusively on software-level mechanisms without dedicated redundant hardware.
The implementation was developed in C++ for an embedded platform running Zephyr RTOS and involved combining multiple sensor readings, fault detection logic, and recovery mechanisms to ensure reliable operation under adverse conditions. This work strengthened my understanding of embedded reliability, real-time systems, and safety-aware firmware design.
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Neuromorphic Engineering
I designed and simulated an analog-domain convolutional neural network for real-time speech feature extraction, targeting ultra-low-power voice activity detection. The system was implemented at transistor level in a 180 nm CMOS technology and focused on exploiting analog computation to minimize power consumption.
The project combined principles from signal processing, neural network architectures, and analog circuit design, highlighting trade-offs between accuracy, power, and silicon area in neuromorphic hardware systems.
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Whinygen
https://github.com/vlelo/whinygenI developed a lightweight white noise generator application written in C89, featuring a graphical user interface built with GTK and audio output handled via SDL. The project emphasized portability, low-level control, and adherence to legacy C standards while maintaining clean structure and usability.
This project reflects my interest in low-level programming, cross-platform software, and building complete, self-contained tools from first principles, integrating signal generation, real-time audio handling, and user interaction.